Question 1. Explain Read operations in 6T based SRAM Memory.

6T-SRAM is one of the most widely used bit-cell. The basic bitcell structure along with read paths are shown below.

 Figure 1: Single bitcell with read path

Figure 2: NMOS Device

Word Line (WL) driver have load cap due to gate cap of access transistor (A1 & A2). Bitline (BL/BLB) have load of metal line & diffusion cap of Access Transistor. These bit-cells are arranged in an array fashion with certain rows and columns normally called as memory array. Memory arrays can be organized into different ways to optimize speed or area. Here you can see one such simple memory array structure (Figure 3).

Figure 3: Bit-cell Array in a Memory

In Figure 3, each square box contains a Bitcell and detailed logic and transistor diagram of the bitcell is provided in below diagram.

Figure 4: 6T-SRAM bit-cell structure

Before we do a read operation, we need to write into each memory cell. For now, let’s assume these bitcells are written with some patterns, we will learn about write operation in a different article. Let’s assume that we have stored value zero i.e. Q = 0V, Qb= VDD (logic value 1) in figure 4.
We want to read this stored data from bitcell. Before we start read we precharge BL and BLB to VDD. To do a read operation we need to turn on the Word Line to VDD (we make a transition on the WL from 0 to VDD) for the selected row out of the several rows arranged in the memory array as shown in figure 3. Once WL is turned ON, gate potential of access (M3 and M4) gate transistor will be at VDD. Both M3 and M1 transistors will be ON and M5 will be OFF as condition as shown in the figure 5 below.

As shown in figure 5, charge stored on the Bitline capacitor will discharge through M3 and M1 transistor. M5 will be OFF during this condition as Qb node has stored VDD value. The capacitor on the Bitline is large and current through the M3 and M1 transistors are small, so discharge on the Bitline will be slow. The node voltage VQ will see a bump (rise of the VQ potential) during the read condition. This bump should not be more than the trip point of the inverter 2 as shown in the figure 3. If the bump or voltage rise is beyond the trip point of the inverter 2, the memory cell will get written during the read condition which is not desirable.

Figure 6: Resistive Model of Transistor Inside Bitcell during Read

The bump or rise of the potential on the node VQ can be understood by equivalent circuit in the figure 6. R3ON and R1ON is the ON resistance of the M3 and M1 transistor respectively. The circuit acts as a potential divider as shown in figure 6.

We need to minimize the value of the R1ON to minimize VQ. So M1 transistor should be sized stronger than M3 transistor.

Let’s review what happens to Bitline bar which stores Qbar to VDD.

As shown in Figure (7), Vds of M4 transistor is 0V, so there are no current through this and Bitline bar remains at precharge level VDD. However, there are small leakage currents discharging the Bitline bar, but this is small compared to the discharge of the Bitline.

Figure 7

So, Bitline discharges due to read current (current through M3 and M1) and Bitline bar remains at VDD. With sufficient time given Bitline level will go down from precharge condition VDD to (VDD-Vdiff) and Bitline bar will remain at VDD.

This differential generated can be sensed by a Sense amplifier (Figure 1) to further amplify small differential generated by bitcell.

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