1.) Find the setup & hold time of X relative to CLK?

Instruction: Logic 1 delay = (3.0ns, 4.0ns)
Delay of Buffer = 2ns
Setup time of Both Flipflop = 2.1ns

Hold Time of Both Flipflop = 2.1ns

Clock-to-Q delay = 1.0ns

A.) 4.1 ns, 0.6 ns

B.) 2.1 ns, 1.5 ns

C.) 0.1 ns, 3.5 ns

D.) None of these

2.) For design to work correctly, what should be maximum hold time of Flip-Flop FF2?

Instruction : Clock period =10 ns
Clock to Q delay = 0 ns
Net delay = 0 ns
Combined logic delay = 11ns A.) 10 ns

B.) 11 ns

C.) 1 ns

D.) None of these

3.) What should be the maximum value of Hold time, so that design work without any Hold violation?
Instruction:  Clock-to-Q Delay = 3.0ns

Net Delay = 0ns
Clock path Delay = 0ns
Time Period = 10ns

A.) 8 ns

B.) 6 ns

C.) 7.5 ns

D.) 4.5 ns

4.) What is the range of Hold time for no Hold violation, if setup time of FF2 = 2.5ns and time period = 10 ns?

Instruction : Clock to Q delay = (1.5 ns, 2.0 ns)
IN1 delay = (0.5 ns, 1 ns)
IN2 delay = (1.1 ns, 2.1 ns)
CL delay = (5.0 ns, 7.5 ns) A.) 0 ns to 4 ns

B.) 4.5 ns to 7 ns

C.) 4.4 ns to 7.5 ns

D.) None of these

5.) There is a Setup Violation in path 3 & Hold Violation in path 2. What is the recommended way to fix the setup Violation?
Instruction: A.) Remove BUF1 from path 2

B.) Add a Buffer in path 1 between OR1 & NAND2

C.) Replace the OR1 with other OR Gate of less maximum delay

D.) Change the clock frequency of the circuit