1. Minimum number of 2-input NAND gates that will be required to implement the function:  Y = AB + CD + EF is

a. 4

b. 5

c. 6

d. 7

2. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed first and on miss, M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is:

a. 4.94 nanoseconds

b. 3.06 nanoseconds

c. 5.0 nanoseconds

d. 5.06 nanoseconds

3. A CPU supports 250 instructions. Each instruction op-code has these fields: The instruction type (one among 250), a conditional register specification, three register operands and an addressing mode specification for both source operands. The CPU has 16 registers and supports 5 addressing modes. What is the instruction op-code length in bits?

a. 32

b. 24

c. 30

d. 36

4. Which of the following equation is true?

a. Tcomb_max <= T(clock) + Tsetup + Tcq + Tskew

b. Tcomb_max >= T(clock) + Tsetup + Tcq + Tskew

c. Tcomb_max >= T(clock) -Tsetup -Tcq –Tskew

d. Tcomb_max <= T(clock) – Tsetup – Tcq + Tskew

5. Which of the following is not a power reduction technique that may be exclusively implemented during the logic synthesis and implementation phase of a chip design process?

a. Clock gating

b. Multi Vt device usage

c. Power Gating

d. Dynamic Voltage and Frequency Scaling

6. What is the output of the following code snippet in simulation?

initial begin
#10 a=1; b = 0;
#10 a=0; b = 1;

end

a. a=1, b=0

b. a=0, b=1

c. a=0, b=0

d. a=1, b=1

7. In the following sequence of non-blocking assignments, what is the value of a, b, c after first evaluation of the assignments?  Assume current value of a=0, b=1, c=2.

a<=1; b<= a; c<= b

a. a=1, b=0, c=1

b. a=0, b=1, c=2

c. a=1, b=1, c=1

d. a=1, b=1, c=2

8. Which of the following equations represent the Sum and Carry operations of a three input adder circuit, the truth table formed by inputs A, B and Ci?

a. S = ∑(1,2,4,7) and C = ∑(3,5,6,7)

b. S = π(1,2,4,7) and C = π(3,5,6,7)

c. S= ∑(1,2,4,7) and C = π(3,5,6,7)

d. S = π(1,2,4,7) and C = ∑(3,5,6,7)

9. Which of the following statement is true about the logic circuit shown below?

i. The circuit may glitch

j. The circuit is used to compute parity for a 5b field

k. The circuit will not glitch

l. The circuit cannot be logically rearranged for bettering timing of signal Y

a. i, j, l

b. j, k, l

c. i, j

d. k, l

10. A one-hot encoding for the states of an FSM is useful for the following purposes

a. Easier RTL design

b. Fault tolerant design

c. Easier ECO-ability

d. Quicker synthesis results

11. Two test chips A and B in the lab exhibit failures – one with hold violations (A) and the other with setup violations (B).  Which of these test chips can carry on functional validation test plans?

a. Both A and B – just reduce frequency

b. Only B – just reduce frequency

c. Only A – just reduce frequency

d. Both A and B – reduce junction temperature

12. Which of the following is not a structural CDC check?

a. Source data stability check

b. The divergence of metastable signals

c. Reconvergence of synchronized signals

d. Divergence in crossover path

  1. Solution: c – 6
  2. Solution: a – 4.94 nanoseconds
  3. Solution: c – 30
  4. Solution: d – Tcomb_max <= T(clock) – Tsetup – Tcq + Tskew
  5. Solution: d – Dynamic Voltage and Frequency Scaling
  6. Solution: b – a=0, b=1
  7. Solution: a – a=1, b=0, c=1
  8. Solution: a – S = ∑(1,2,4,7) and C = ∑(3,5,6,7)
  9. Solution: c – i,j
  10. Solutions: b – Fault tolerant design
  11. Solution: b – Only B – just reduce frequency
  12. Solution: a – Source data stability check

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