1.) Above diagram is corresponds to PMOS device. Kindly identify region A?

Instruction :

A.) Pwell

B.) Nwell

C.) p+ area

D.) P-substrate

2.) In what cases above structure can be a PMOS device?

Instruction :

A.) Region A : p+ , Region B : p+, Region C : p+

B.) Region A : n+ , Region B : n+, Region C : p+

C.) Region A : n+ , Region B : p+, Region C : p+

D.) None of these

3.) What do you mean by SOI?

A.) Silicon On Chip

B.) Silicon On Insulator

C.) Silicon Of Insulator

D.) Semiconductor on Insulator

4.) Which of the following statement is/are correct for STI (Shallow Trench Isolation)?

A.) It creates a connection with Shallow points in the design

B.) It’s an Insulation between active devices

C.) It’s present in the Substrate region.

D.) It’s filled with SiO2

5.) Below is a layout of MOS device. Identify different region?

A.) Region a: Source, Region b: Gate, Region c: Drain

B.) Region a: Source, Region b: Drain, Region c: Gate

C.) Region a: Drain, Region b: Gate, Region c: Source

D.) Region a: Gate, Region b: Drain, Region c: Source

6.) What are the possible regions of above layout if it’s related to NMOS devices?

Instruction :

A.) Region a: Source, Region b: Gate, Region c: Drain, Region d: Gate, Region e: Source

B.) Region a: Drain, Region b: Gate, Region c: Source, Region d: Gate, Region e: Source

C.) Region a: Drain, Region b: Gate, Region c: Source, Region d: Gate, Region e: Drain

D.) Region a: Gate, Region b: Source, Region c: Gate, Region d: Drain, Region e: Gate

7.) What is the output of following connection of switches?

A.) y = a+b

B.) y = a.b

C.) 1

D.) 0

8.) What is the output of following connection of switches?

A.) y = a.b

B.) y = a+b

C.) 1

D.) 0

9.) What would be the voltage on other nodes if the threshold voltage of NMOS is Vtn?

A.) VDD

B.) VDD – Vtn

C.) 0

D.) Vtn

10.) NMOS is a

A.) Good 0

B.) Poor 0

C.) Good 1

D.) Poor 1

11.) If VDD = 3.3 V and Vtn= 0.55V

Vin = 3.1 V , Vout =?

A.) 0.55V

B.) 3.1V

C.) 2.2V

D.) 2.75V

12.) What would be the voltage on node A and B, if the threshold voltage of NMOS is V?

A.) VDD, VDD

B.) VDD – Vtn, VDD – Vtn

C.) 0, 0

D.) Vtn , Vtn

E.) VDD – Vtn, VDD – 3Vtn

13.) Initial voltage of 0.51V on all the internal Nodes. Find out the voltages at C and E node If VDD = 1V, Vtn = 0.3V?

A.) 1.0V, 1.0V

B.) 0.7V, 0.7V

C.) 0.3V, 0.3V

D.) 0.7V, 0.6V

E.) 0.4V, -0.3V

Answers

1.) B

2.) D

3.) B

4.) B, C, D

5.) A, C

6.) A, C

7.) A

8.) A

9.) B

10.) A, D

11.) D

12.) B

13.) D

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