1. Familiarizing basic concepts about Clock Domain Crossing
1.1. Synchronous and asynchronous domains
In synchronous systems, the clock that operates on different logic is generated from the same source. The main clock is generated from one clock source and other clocks are derived from the main clocks, for example, CLK/2, CLK/4 are generated from one main clock called CLK.
Fig.1: Synchronous domain
In an asynchronous system, the clocks are originated from the different source. Here the phase shift of the clocks is different.
1.2. Metastability issue
In a metastable state, the flip-flop output enters into an unpredictable state, the flip-flop output oscillates between 0 and 1. Due to setup and hold issues in flip-flops, the flop output enters into a state where the output is unpredictable, and the output reaches a final stable value 0 or 1.
2. What are clock domain crossing (CDC) and CDC issues
The signal passing from one clock domain to another clock domain is known as clock domain crossing (CDC). In another word, an asynchronous signal entering into another clock domain logic is called clock domain crossing. The signal entering from one domain to another different domain need to be synchronized with respect to receiving clock before passing to any logic inside the receiver clk domain otherwise it can lead to clock domain crossing issues.
Depending on “entering signal “, the signal can be a single bit or multi-bit, we need to design the synchronous logic. We need to understand some logical concepts and need to follow some design guidelines before going for an actual design.
3. CDC Design guidelines
3.1. Double synchronization (control path)
A double synchronizer is used to avoid the metastability issue while a signal crossing from one domain to another domain. The signal Din_b is the output of ACLK domain signal and reaching to BCLK domain.
Fig.2. Double synchronizer
What issues are faced with above example?
- The Din_b signal is asynchronous input in BCLK domain?
- Are there any metastability issues?
- Are there any functional simulation issues?
- What happens if there are no synchronizer?
Let’s analyze these questions listed above in more detail
If the signal Din_b to the BCLK domain toggles from (0->1 or 1->0) during the rising edge of the BCLK the first flop output goes to metastable due to timing violations. This can lead to potential functionality violation if there is no proper synchronization. Let’s review how synchronizer will help to resolve this issue. The second flop input has enough time to converge from metastable state to a stable value then the second flop output will solve the problem and BCLK domain logic will get a stable value.
These issues cannot be highlighted with an ideal functional simulation tool. It requires separate CDC tool (e.g. Mentor CDC).
Q1. Are two stage synchronizers enough to solve this problem?
Q2. If the control signal is a pulse synchronizer, will it solve the problem or any extra logic is required to solve this?
3.2. Convergence issue
Let’s discuss what happens when a combinational output crosses from one domain to another domain.
Fig.3. Convergence issue
The example mentioned in Fig.3 shows the signal from a combinational block (like AND or AND_OR logic) crossing from Tx domain to Rx Domain. This can create glitches and timing violation tool can’t detect this violation. Rx will sample wrong signal value even though if there is a proper synchronizer.
To avoid that synchronize the two signal Out1 and Out2 separately in Rx domain before doing any operation or proper design consideration need to take care.
Q3. Why the tool is not able to detect the timing violations?
Q4. What are the possible design considerations needs to be taken care to avoid convergence issues?
Summary of the post
- Meta-stability issues and clock domains
- Proper synchronizer should be placed in between control path
- Before passing the signal from one domain to another make sure the crossing signals are coming from sequential blocks.
Topics for the next posts
- Divergence and re-convergence issues
- Pulse signal crossing from low to high asynchronous clocks and high to low asynchronous clocks
- Data signal synchronizer methods (e.g. Async FIFO)
- Reset synchronizers