In a 6T-SRAM (Figure 1), node Q value determines the data stored in bit-cell. If value of node Q (VQ) is VDD, then data stored in bit-cell is 1 (one). Similarly, if VQ= 0V, then stored value in bit-cell is 0 (zero).

Figure 1. Structure of bit-cell

Let’s say we want to write a data 1 in a bit-cell where stored value is 0. Data, which we want to write, should be set on bit-line before Word Line (WL) gets turned ON. To write data logic-1 (VDD), BL should be VDD (logic-1) and BLB should be 0V (logic 0) as shown in figure 2.

Figure 2. Value of BL & BLB to write data 1

Once, WL turns ON, Current I1 flows through access transistor N3, which in turn tries to accumulate charge on Node Q. Pull down NMOS (N1) has current I2, which tries to discharge this accumulated charge as shown in below figure 3.

Figure 3. State of Bit-cell during write (BL)

As we have seen that Access transistor is sized weaker than pull-down NMOS of bit-cell to avoid read failure stability.  So, I2 > I1, hence there will be no accumulation of charge on Node Q (such that Vq > Vm , Vm – switching threshold of Inverter) to facilitate writing of data in bit-cell. So we have to use other differential pair of bit-line to write data, as shown in figure 4.

Once WL turns ON, Access transistor (N4) tries to discharge node Qb, whereas Pull-PMOS (P2) charges Node Qb to VDD (logic-1). Clearly, there is fight between Pull-up PMOS and Access transistor NMOS (Figure 4-a). If we want to write data in bit-cell, Access transistor NMOS should win this fight.  As we know, NMOS is stronger than PMOS. So NMOS should be able to discharge the node Qb. Once Qb starts to discharge it slightly turns on pull-up PMOS P1 & slightly turns off NMOS N1 of other cross-coupled Inverter. Once, Access transistor N4 discharges node Qb completely, PMOS P1 is fully turned ON and NMOS N1 is turned OFF , and thus node Q will be charged up at potential VDD. (Figure 4-b). Thus, we will be writing data successfully.



Figure 4. (a) State of Bit-cell during write (BLB) and (b) Flip of internal node in bit-cell

But, we should be able to write in the worst case as well.  Can you name the worst case? Fight (Contention) between PMOS & access NMOS will be worst when NMOS is weaker and PMOS is stronger due to process variations. Hence, SF corner will be the worst for write-ability. In order to ensure successful write in SF corner as well, Access transistor NMOS will be sized more compared to Pull-up PMOS transistor i.e. size of Access NMOS > PMOS.


Please enter your comment!
Please enter your name here