Wednesday, May 22, 2019

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    Interview Questions For Logic Design

    Minimum number of 2-input NAND gates that will be required to implement the function:  Y = AB + CD + EF is a. 4 b. 5 c. 6 d. 7 2. Consider a two-level memory hierarchy system M1 &...

    Interview Questions for Digital Electronics

    1.) In a Hexa-decimal system, (77) 16 – (3B)16 is equal to? A.) (3D)16 B.) (60)16 C.) (3C)16 D.) (73)16 2.) What is the output of following switch network? 3.) If this circuit is considered as 4 Bit full adder, which takes 42ns...

    Automation in Layout Design

    We have come a long way since the days when CAD Engineers used to draw layouts on Graph papers. Sophisticated tools with multiple utilities to draw, verify and correct the layouts, and enhanced ‘User...
    Clock Domain

    Clock Domain Crossing

    1. Familiarizing basic concepts about Clock Domain Crossing   1.1.       Synchronous and asynchronous domains In synchronous systems, the clock that operates on different logic is generated from the same source. The main clock is generated...

    Bitcell Write

    In a 6T-SRAM (Figure 1), node Q value determines the data stored in bit-cell. If value of node Q (VQ) is VDD, then data stored in bit-cell is 1 (one). Similarly, if VQ= 0V,...

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