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    Interview Questions For Logic Design

    Minimum number of 2-input NAND gates that will be required to implement the function:  Y = AB + CD + EF is a. 4 b. 5 c. 6 d. 7 2. Consider a two-level memory hierarchy system M1 &...

    Interview Questions for Digital Electronics

    1.) In a Hexa-decimal system, (77) 16 – (3B)16 is equal to? A.) (3D)16 B.) (60)16 C.) (3C)16 D.) (73)16 2.) What is the output of following switch network? 3.) If this circuit is considered as 4 Bit full adder, which takes 42ns...

    Interview Questions for Semiconductor Theory

    1.) How many depletion layers are present in the figure shown below? A.) 8 B.) 6 C.) 10 D.) 5 2.) Identify the number of P-N junction (diodes) in the below picture? A.) 5 B.) 0 C.) 2 D.) none of these 3.) If we increase, voltage...
    Clock Domain

    Clock Domain Crossing

    1. Familiarizing basic concepts about Clock Domain Crossing   1.1.       Synchronous and asynchronous domains In synchronous systems, the clock that operates on different logic is generated from the same source. The main clock is generated...

    Interview Questions for CMOS

    1.) Above diagram is corresponds to PMOS device. Kindly identify region A? Instruction : A.) Pwell B.) Nwell C.) p+ area D.) P-substrate 2.) In what cases above structure can be a PMOS device? Instruction : A.) Region A : p+ ,...

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