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    Interview Questions for CMOS

    1.) Above diagram is corresponds to PMOS device. Kindly identify region A? Instruction : A.) Pwell B.) Nwell C.) p+ area D.) P-substrate 2.) In what cases above structure can be a PMOS device? Instruction : A.) Region A : p+ ,...

    Interview Questions for Semiconductor Theory

    1.) How many depletion layers are present in the figure shown below? A.) 8 B.) 6 C.) 10 D.) 5 2.) Identify the number of P-N junction (diodes) in the below picture? A.) 5 B.) 0 C.) 2 D.) none of these 3.) If we increase, voltage...

    Layout Verification: Apply Systematic Approach

    It was Wednesday morning when I approached my Manager for a discussion on my next assignment. We had delivered a project in the past week and after relaxing for a couple of days, we were...

    Interview Questions For Logic Design

    Minimum number of 2-input NAND gates that will be required to implement the function:  Y = AB + CD + EF is a. 4 b. 5 c. 6 d. 7 2. Consider a two-level memory hierarchy system M1 &...

    Interview Questions for Timing Concepts

    1.) Find the setup & hold time of X relative to CLK? Instruction: Logic 1 delay = (3.0ns, 4.0ns) Delay of Buffer = 2ns Setup time of Both Flipflop = 2.1ns Hold Time of Both Flipflop = 2.1ns Clock-to-Q delay...

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