Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is
2. Consider a two-level memory hierarchy system M1 &...
1.) In a Hexa-decimal system, (77) 16 – (3B)16 is equal to?
2.) What is the output of following switch network?
3.) If this circuit is considered as 4 Bit full adder, which takes 42ns...
1.) How many depletion layers are present in the figure shown below?
2.) Identify the number of P-N junction (diodes) in the below picture?
D.) none of these
3.) If we increase, voltage...
1. Familiarizing basic concepts about Clock Domain Crossing
1.1. Synchronous and asynchronous domains
In synchronous systems, the clock that operates on different logic is generated from the same source. The main clock is generated...
1.) Above diagram is corresponds to PMOS device. Kindly identify region A?
C.) p+ area
2.) In what cases above structure can be a PMOS device?
A.) Region A : p+ ,...
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